/* SPDX-License-Identifier: GPL-2.0 */
/*
 * Author   : Ryan Shen
 * Contract : shentao@huawei.com
 * File     : hw_drv_dev.h
 * Describe : hisilicon device driver.
 * Platform : ARM Cortex-A9 & Linux 2.6.34.10
 * Log      : 2018-03-20 : init version completed.
 *
 * Copyright (c) 2010-2012 by Hisilicon. All rights reserved.
 */

#ifndef	__HW_DRV_DEV_H__
#define	__HW_DRV_DEV_H__
#include <linux/skbuff.h>
#include <linux/pci.h>
#ifndef KER_F_DESC
#define KER_F_DESC(x) 1
#endif

#ifndef HW_RET_SUCCESS
#define HW_RET_SUCCESS (0)
#endif

#define CHIP_ID_SERIAL_VERSION_MASK     (0xfffff000)
#define CHIP_ID_SERIAL_MASK             (0xffff0000)
#define CHIP_ID_VERSION_MASK            (0xf000)
#define CHIP_ID_SUB_VERSION_MASK        (0xffffff00)
#define CHIP_ID_ALL_VERSION_MASK        (0xfffffff0)

/* SERIAL_VERSION after the mask of CHIP_ID_SERIAL_VERSION_MASK,not care the last 3 bits */
#define CHIP_ID_SD5115H    (0x51150000)
#define CHIP_ID_SD5115S    (0x51151000)
#define CHIP_ID_SD5115T    (0x51152000)

#define CHIP_ID_SD5116H    (0x51160000)
#define CHIP_ID_SD5116S    (0x51161000)
#define CHIP_ID_SD5116T    (0x51162000)
#define CHIP_ID_SD5116TV5  (0xD53EA000)
#define CHIP_ID_SD5116L    (0x51163000)

#define CHIP_ID_SD5118    (0x51180100)
#define CHIP_ID_SD5118V2  (0x51180200)
#define CHIP_ID_SD5117H   (0x51170000)
#define CHIP_ID_SD5117L   (0x51173000)
#define CHIP_ID_SD5117P   (0x51176000)
#define CHIP_ID_SD5117V   (0x51177000)
#define CHIP_ID_SD5117V_V6 (0x87607100)
#define CHIP_ID_SD5117P_V5 (0xE536E100)
#define CHIP_ID_SD5182H_V5 (0x95409430)
#define CHIP_ID_SD5182S_V5 (0xD9969000)
#define CHIP_ID_SD5182T   (0x51822100)
#define CHIP_ID_SD5182TCS (0x38322000)

#define CHIP_ID_SD5182H   (0x51820000)
#define CHIP_ID_SD5182S   (0x51821000)
#define CHIP_ID_SD5610H   (0x56100000)
#define CHIP_ID_SD5610T   (0x56102000)
#define CHIP_ID_SD1156H   (0x56120000)
#define CHIP_ID_SD5190    (0x51900000)
#define CHIP_ID_SD1155H   (0x00050000)
#define CHIP_ID_SD1156EH  (0x11560000)
#define CHIP_ID_SD2952H   (0x29520000)

/* serial after the mask of CHIP_ID_SERIAL_MASK,not care the last 4 bits */
#define CHIP_ID_SD5115_SERIAL   (0x51150000)
#define CHIP_ID_SD5116_SERIAL   (0x51160000)
#define CHIP_ID_SD5118_SERIAL   (0x51180000)
#define CHIP_ID_SD5117_SERIAL   (0x51170000)
#define CHIP_ID_SD5117_SERIAL_V6   (0x87600000)
#define CHIP_ID_SD5182_SERIAL   (0x51820000)
#define CHIP_ID_SD1156_SERIAL   (0x56120000)
#define CHIP_ID_SD5190_SERIAL   (0x51900000)
#define CHIP_ID_SD1155_SERIAL   (0x00050000)
#define CHIP_ID_SD1156E_SERIAL  (0x11560000)
#define CHIP_ID_SD2952_SERIAL   (0x29520000)

/* version after the mask of CHIP_ID_VERSION_MASK,not care the last 3 bits */
#define CHIP_ID_H_VERSION   (0x0000)
#define CHIP_ID_S_VERSION   (0x1000)
#define CHIP_ID_T_VERSION   (0x2000)
#define CHIP_ID_L_VERSION   (0x3000)

#define BOARD_INIT_SECTION_MAX_LEN     (48)          /* section */
#define BIT_MOVE_32                    (32)
#define BITMASK_LOW32                  (0xffffffff)
/* [1, 100], [1, 400] */
#define SRC_I2C_BAUD_RATE_45K  (45)

#define WRITEL_ORR(data, addr) writel((readl(addr) | (data)), (addr))
#define WRITEL_AND(data, addr) writel((readl(addr) & (data)), (addr))

// sd5115 kernel export functions
enum HW_CHIP_ID_E {
	HW_CHIP_ID_NONE_E = 0x0,
	HW_CHIP_ID_5115S_E,
	HW_CHIP_ID_5115H_E,
	HW_CHIP_ID_5115T_E,
	HW_CHIP_ID_5116S_E,
	HW_CHIP_ID_5116H_E,
	HW_CHIP_ID_5116T_E,
	HW_CHIP_ID_5116L_E,
	HW_CHIP_ID_5118_E,
	HW_CHIP_ID_5118V2_E,
	HW_CHIP_ID_5117H_E,
	HW_CHIP_ID_5117P_E,
	HW_CHIP_ID_5610H_E,
	HW_CHIP_ID_5610T_E,
	HW_CHIP_ID_5117V_E,
	HW_CHIP_ID_5117L_E,
	HW_CHIP_ID_5182H_E,
	HW_CHIP_ID_5182S_E,
	HAL_CHIP_ID_5117PV5,
	HAL_CHIP_ID_5182HV5,
	HAL_CHIP_ID_5182T,
	HAL_CHIP_ID_5182SV5,
	HW_CHIP_ID_5116TV5_E,
	HAL_CHIP_ID_1156H,
	HAL_CHIP_ID_1156E,
	HAL_CHIP_ID_5190,
	HAL_CHIP_ID_1155H,
	HAL_CHIP_ID_2952H,
	HW_CHIP_ID_MPW_E,
};

struct hw_ker_chipid_info_s {
	uint32_t ui_chip_mask;    /* chip reg mask */
	uint32_t ui_chip_value;   /* masked chip reg */
	enum HW_CHIP_ID_E em_chip_id; /* chip id */
};

struct dev_pcie_test_s {
	uint32_t ui_pcie_id;    // pcie0 or pcie1
	uint32_t ui_pcie_opt;   // loopback enable or disable or test start
	uint32_t ui_pcie_size;  // test data size
	uint32_t ui_pcie_times; // test times
	uint32_t chip_id;
};


extern enum HW_CHIP_ID_E hw_chip_id;
enum HW_CHIP_ID_E hw_kernel_get_chip_id(void);
bool is_sd5117p_series(void);

/* GPIO value */
enum src_gpio_value {
	GPIO_IO_LOW = 0,         /* 0 */
	GPIO_IO_HIGH,            /* 1 */
	GPIO_IO_HIGH_RESISTANCE, /* resist */
	GPIO_IO_BUTT
};

/* GPIO direction */
enum src_gpio_direct {
	GPIO_DIRECT_INPUT = 0, /* input */
	GPIO_DIRECT_OUTPUT,    /* output */
	GPIO_DIRECT_BUTT
};

enum src_i2c_work_mode {
	I2C_WORK_MODE_MASTER,  /* master */
	I2C_WORK_MODE_SLAVE,   /* slave */
	I2C_WORK_MODE_MBUS,    /* MBUS */
};

/* read/write mode */
enum src_i2c_rw_mode {
	I2C_RW_MODE_NORMAL,
	I2C_RW_MODE_EXTERN,
	I2C_RW_MODE_BUTT
};

struct src_gpio_id_ctrl {
	uint32_t chip_id;
	uint32_t ui_id; /* GPIO id */
	union {
		uint32_t ui_mode;   /* GPIO mode */
		uint32_t ui_direct; /* GPIO direction */
		uint32_t ui_value;  /* GPIO value */
	} ctrl_data;
};

/* ability */
struct src_gpio_ability {
	uint32_t chip_id;
	uint32_t pin_id;
	uint32_t value;
};

struct src_i2c_dev_info {
	uint8_t dev_type; /* i2c_dev_type */
	uint8_t dev_type_idx;
	uint8_t rw_mode;  /* kernel_i2c_rw_mode */
	uint8_t chip_id;  /* i2c_chip_type */
};

/* section parse */
struct src_ini_section_parse {
	uint8_t key_word[BOARD_INIT_SECTION_MAX_LEN];
	uint32_t value;
};

struct hardware_timer_attr {
	uint32_t enable;
	uint32_t period;
	uint32_t usec;
	void *para;
	void (*pf_call_back)(void *args);
};

enum pcie_link_speed {
	PCIE_LINK_SPEED_NO,
	PCIE_LINK_SPEED_1D1,
	PCIE_LINK_SPEED_2D,
	PCIE_LINK_SPEED_3D,
	PCIE_LINK_SPEED_4D,
};

enum pcie_link_quality {
	PCIE_LINK_QA_NO,
	PCIE_LINK_QA_POOR,
	PCIE_LINK_QA_GOOD,
};

struct pcie_link_state_info {
	uint8_t index;
	enum pcie_link_speed speed;
	enum pcie_link_width width;
	enum pcie_link_quality quality;
};

typedef uint32_t (*gpio_set_direct_funcptr)(const struct src_gpio_id_ctrl *gpio_ctrl);
typedef uint32_t (*gpio_set_ability_funcptr)(const struct src_gpio_ability *gpio_ability);
typedef uint32_t (*gpio_write_data_funcptr)(const struct src_gpio_id_ctrl *gpio_ctrl);
typedef uint32_t (*gpio_get_sw_bit_funcptr)(uint32_t chip_id, uint8_t gpio_id, uint32_t *value);

typedef void (*pcie_dfx_reocrd_funcptr)(void);
typedef uint32_t (*i2c_read_data_funcptr)(
	const struct src_i2c_dev_info *dev_info, uint16_t dev_addr, uint32_t reg_addr,
	uint32_t addr_len, uint8_t *read_buff, uint32_t buff_len
);
typedef uint32_t (*i2c_write_data_funcptr)(
	const struct src_i2c_dev_info *dev_info, uint16_t dev_addr, uint32_t reg_addr,
	uint32_t addr_len, const uint8_t *write_data, uint32_t data_len
);

typedef uint32_t (*i2c_set_speed_funcptr)(const struct src_i2c_dev_info *dev_info,
	uint32_t baud_rate);
typedef uint32_t (*i2c_set_work_mode_funcptr)(const struct src_i2c_dev_info *dev_info,
	enum src_i2c_work_mode work_mode);

typedef uint32_t (*get_section_cfg_funcptr)(uint8_t *section,
	const struct src_ini_section_parse *section_cfg, uint32_t section_cfg_num);

typedef uint32_t (*drv_common_file_read_funcptr)(const char *file_name,
	char *content, uint32_t size);
typedef uint32_t (*drv_common_file_write_funcptr)(uint8_t *input,
	uint8_t *output, uint32_t out_len);
typedef uint32_t (*drv_common_reset_funcptr)(char *file_name, const char *content, uint32_t size);

typedef uint32_t (*pcie_link_speed_info_get_funcptr)(struct pcie_link_state_info *info,
	uint32_t info_size, uint32_t *pcie_num);

typedef void (*close_pcie_funcptr)(void);
typedef uint32_t (*pcie_test_funcptr)(void *test_data);

typedef uint32_t (*feature_issupport_funcptr)(const char *pc_ft_name);
typedef int32_t  (*src_radio_skb_handler)(struct sk_buff *skb);
typedef uint32_t (*serdes_lane_init_funcptr)(uint32_t chip,
	uint64_t xport, uint32_t lane, uint32_t mode);
typedef uint32_t (*nvme_custom_flush_funcptr)(char *nvme_dev, uint32_t timeout_ms);
typedef uint32_t (*dev_hardware_timer_set)(struct hardware_timer_attr *attr, uint32_t *timer_id);

struct gpio_drv_func {
	gpio_set_direct_funcptr gpio_drv_set_direct_hook;
	gpio_set_ability_funcptr gpio_drv_set_ability_hook;
	gpio_write_data_funcptr gpio_drv_write_data_hook;
	gpio_get_sw_bit_funcptr gpio_drv_get_sw_bit_hook;
};

struct i2c_drv_func {
	i2c_read_data_funcptr i2c_drv_read_data_hook;
	i2c_write_data_funcptr i2c_drv_write_data_hook;
	i2c_set_speed_funcptr i2c_drv_set_speed_hook;
	i2c_set_work_mode_funcptr i2c_drv_set_work_mode_hook;
};

struct dev_drv_func {
	dev_hardware_timer_set set_hardware_time;
};

struct pcie_dfx_func {
	pcie_dfx_reocrd_funcptr pcie_dfx_record;
};

struct gpio_drv_func *get_gpio_func_hook(void);
struct i2c_drv_func *get_i2c_func_hook(void);
struct dev_drv_func *get_dev_drv_func(void);
struct pcie_dfx_func *get_pcie_dfx_record_func_hook(void);
get_section_cfg_funcptr *get_section_cfg_func_hook(void);
close_pcie_funcptr *get_close_pcie_func_hook(void);
pcie_test_funcptr *get_pcie_test_func_hook(void);
feature_issupport_funcptr *get_feature_issupport_func_hook(void);
src_radio_skb_handler **get_radio_rx_handler(void);
unsigned long hw_kallsyms_lookup_name(const char *name);

drv_common_file_read_funcptr *get_drv_common_file_read_func_hook(void);
drv_common_file_write_funcptr *get_drv_common_file_write_func_hook(void);
drv_common_reset_funcptr *get_drv_common_reset_func_hook(void);
serdes_lane_init_funcptr *get_serdes_lane_init_func_hook(void);
pcie_link_speed_info_get_funcptr *get_pcie_link_speed_info_func_hook(void);
void set_pcie_link_speed_info_func_hook(pcie_link_speed_info_get_funcptr func);
void ker_nvme_custom_flush_hook_set(nvme_custom_flush_funcptr func);
#endif
